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XRD64L42
Dual 10-Bit 40MSPS CMOS ADC
January 2001-1
FEATURES
APPLICATIONS
* 10-Bit Resolution * Two Monolithic Complete 10-Bit ADCs * * * * * * * * * * *
40 MSPS Conversion Rate On-Chip Track-and-Hold On-Chip Voltage Reference Low 5 pF Input Capacitance TTL/CMOS Outputs Tri-State Output Buffers Single +3.0V Power Supply Operation Low Power Dissipation: 200mW-typ @ 2.7V Power Down Mode Less Than 5mW 75dB Crosstalk (fin=1.0MHz) -40C to +85C Operation Temperature Range
* Medical Ultrasound Imaging * I & Q Modems
BENEFITS
* * * *
Reduction of Components Reduction of System Cost High Performance @ Low Power Dissipation Long Term Time and Temperature Stability
GENERAL DESCRIPTION The XRD64L42 is two 10-bit, monolithic, 40 MSPS ADCs. Manufactured using a standard CMOS process, the XRD64L42 offers low power, low cost and excellent performance. The on-chip track-and-hold amplifier(T/H) and voltage reference (VREF) eliminate the need for external active components, requiring only an external ADC conversion clock for the application. The XRD64L42 analog input can be driven with ease due to the high input impedance. The design architecture uses 17 time- interleaved 10bit SAR ADCs in each converter to achieve high conversion rate of 40 MSPS minimum. In order to insure and maintain accurate 10-bit operation with respect to time and temperature, XRD64L42 incorporates an auto-calibration circuit which continuously adjusts and matches the offset and linearity of each ADC. This auto-calibration circuit is transparent to the user after the initial 3.4ms calibration (168,000 initial clock cycles). The power dissipation is only 200mW at 40 MSPS with +2.7V power supply. The digital output data is straight binary format, and the tri-state disable function is provided for common bus interface. The XRD64L42 internal reference provides cost savings and simplifies the design/development. The output voltage of the internal reference is set by two external resistors. The internal reference can be disabled if an external reference is used for a power savings of 50mW.
ORDERING INFORMATION
Part Number XRD64L42AIV Package Type 64-Lead TQFP Temperature Range -40C to +85C
Rev. P2.10
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017
XRD64L42
VINA+VINA-
Bandgap
10 Bit A/D's
ADC A
A/D 1a
VBG
VFBK VRHF
+
A/D 17a
11
DA9 - DA0, OTRA TRI_A DIFF SYNCO PD CKIN
K
CONTROL LOGIC
10 Bit A/D's
ADC B
A/D 1b
VRLF
11
VCMO
+
DB9 - DB0, OTRB TRI_B
A/D 17b
VINB+VINB-
Figure 1. XRD64L42 Simplified Block Diagram
Rev. P2.10
2
XRD64L42
DOGND DOVDD
DGND DVDD
OTRA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VCMO DB9 DB8 DB7 DB6 DB5 DB4 DB3
26 49
OTRB
33 32 27 28 29 30 31
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DGND AGND AVDD AGND AGND VINBVINB+
56 55 54 53 52 51 50
DA0
XRD64L42 64QFP
DGND
25 24 23 22 21 20 19 18
AGND VINA+ VINAAGND AVDD AVDD AGND AGND
64 1 2 3 4 5 6 7 63 62 61 60 59 58 57
DOVDD DOGND DB2 DB1 DB0 SYNCO CKIN TRI_A
17
8
9
10
11
12
13
14
15
16
VFBK
VBG
VRLF
VRLF
PD AGND AGND AGND
DVDD
VRHF
VRHF
DGND
DGND
Rev. P2.10
3
AGND TRI_B DIFF
XRD64L42
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Symbol VBG VFBK VRHF VRHF VRLF VRLF AGND AGND AGND DGND DGND PD DVDD TRI_B DIFF AGND TRI_A CKIN SYNCO DB0 DB1 DB2 DOGND DOVDD DGND DB3 DB4 DB5 DB6 DB7 DB8 DB9 OTRB DA0 DA1 DA2 DA3 DA4 DOVDD DOGND DVDD Description Bandgap Voltage Output Analog Reference Feedback Top Voltage Reference Force Top Voltage Reference Force Bottom Voltage Reference Force Bottom Voltage Reference Force Analog Ground Analog Ground Analog Ground Digital Ground Digital Ground Power Down, Active High Digital Supply Voltage Tri-state for the B Channel Outputs, Active High Hi=Differential Mode, Lo=Single-Ended Mode Analog Ground Tri-state for the A Channel Outputs, Active High Clock Input Data Valid Output (Rising Edge) Digital Output Bit 0 (LSB) ADC B Digital Output Bit 1 ADC B Digital Output Bit 2 ADC B Digital Output Ground Digital Output Supply Voltage Digital Ground Digital Output Bit 3 ADC B Digital Output Bit 4 ADC B Digital Output Bit 5 ADC B Digital Output Bit 6 ADC B Digital Output Bit 7 ADC B Digital Output Bit 8 ADC B Digital Output Bit 9 (MSB) ADC B Over Range Digital Output Bit ADC B Digital Output Bit 0 (LSB) ADC A Digital Output Bit 1 ADC A Digital Output Bit 2 ADC A Digital Output Bit 3 ADC A Digital Output Bit 4 ADC A Digital Output Supply Voltage Digital Output Ground Digital Supply Voltage
Rev. P2.10
4
XRD64L42
PIN DESCRIPTION (CONT'D)
Pin # 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol DGND DA5 DA6 DA7 DA8 DA9 OTRA VCMO DGND AGND AVDD AGND AGND VINBVINB+ AGND VINA+ VINAAGND AVDD AVDD AGND AGND Description Digital Ground Digital Output Bit 5 ADC A Digital Output Bit 6 ADC A Digital Output Bit 7 ADC A Digital Output Bit 8 ADC A Digital Output Bit 9 ADC A Over Range Digital Output Bit ADC A Differential Common Mode Voltage Output Digital Ground Analog Ground Analog Supply Voltage Analog Ground Analog Ground Analog Input B(-) Analog Input B(+) Analog Ground Analog Input A(+) Analog Input A(-) Analog Ground Analog Supply Voltage Analog Supply Voltage Analog Ground Analog Ground
Rev. P2.10
5
XRD64L42
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40 MSPS, 50% Duty Cycle, Differential Input Mode
Symbol Parameter Min. Typ. Max. Unit Conditions
DC ACCURACY DNL INL MON FSE ZSE Differential Non-Linearity Integral Non-Linearity Monotonicity Full Scale Error Zero Scale Error -0.75 +/-0.25 +/-0.5 No Missing Codes +10 5 mV mV .75 LSB LSB Guaranteed by Test F.S. = (VRHF - VRLF)x0.97 Single Ended Mode
1
ANALOG INPUT INVR INRES INCAP INBW Input Voltage Range Input Resistance Input Capacitance Input Bandwidth 1 20 5 400
VRHFx0.97
V KOhms pF MHz
VRLF Grounded
-1dB Small Signal
REFERENCE INPUT, INTERNAL BANDGAP REFERENCE AND REFERENCE BUFFER RLAD RLADTCO VBG Ladder Resistance Ladder Resistance Tempco Bandgap Output Voltage Range VBGTC Bandgap Reference Tempco VRLF VRHF VRHF External Reference 0.0 VRLF+ 1.0 VRLF+ 1.0 VRHF PSRR Internal Reference Buffer VCMO, Common Mode Voltage VCMO Isource Common Mode Voltage Current Source 1.15 200 1.25 500 1.35 V uA 6 mV/V 2.5 AVdd V External 0.0 2.0 AVdd-0.3 V V Internal Reference Buffer 30 ppm/C 1.15 100 125 +0.8 1.25 1.35 150 Ohms Ohms/C V
Notes:
1
There is a series resistor (approximately 3 to 4 ohms) between VRHF and the ladder resistance. The voltage drop associated with this series resistance accounts for the 0.97 multiplication factor.
Rev. P2.10
6
XRD64L42
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40MSPS, 50% Duty Cycle, Differential Input Mode
Symbol Parameter Min. Typ. Max. Unit Conditions
DYNAMIC PERFORMANCE Fs = 40MHz SNR Signal-to-Noise Ratio fin = 1.0 MHz fin = 4.0 MHz fin = 10.0 MHz SINAD Signal-to Noise and Distortion fin = 1.0 MHz fin = 4.0 MHz fin = 10 MHz ENOB EFFECTIVE NUMBER OF BITS fin = 1.0 MHz fin = 4.0 MHz fin = 10 MHz SFDR SPURIOUS FREE DYNAMIC RANGE SFDR Crosstalk IMD fin = 1.0 MHz fin = 1.0 MHz fin1 = 2.5 MHz fin2 = 3.5 MHz CONVERSION AND TIMING CHARACTERISTICS (CL = 10pF) MAXCON MINCON Lat APJT tr tf tpd tden tdis CLKDC Maximum Conversion Minimum Conversion Latency Aperture Jitter Time Digital Output Rise Time Digital Output Fall Time Output Data Propagation Delay Output Data Enable Delay Output Data Disable Delay Clock Duty Cycle 40 50 60 % Guaranteed by Design 5 20 ns Guaranteed by Design 6 20 ns Guaranteed by Design 40 50 100 17 12 3 3 6 25 MSPS KSPS cycles ps ns ns ns Guaranteed by Design Peak-to Peak 70 75 70 dB dB dB Intermodulation Distortion 9.3 9.2 9.0 9.7 9.5 9.2 Bit Bit Bit 58 57 56 60 59 58 dB dB dB 58 57 57 60 60 59 dB dB dB Including Harmonics Not Including Harmonics
Rev. P2.10
7
XRD64L42
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40 MSPS, 50% Duty Cycle, Differential Input Mode
Symbol DVINH DVINL DIINH CKIN DIFF TRI_A/TRI_B PD DIINL CKIN DIFF TRI_A/TRI_B PD DINC DOHV DOLV IOZ Parameter Digital Input High Voltage Digital Input Low Voltage Digital Input High Leakage Clock Input Differential/Single-Ended Input A/B Channel Tri-State Power Down Digital Input Low Leakage Clock Input Differential/Single-Ended Input A/B Channel Tri-State Power Down Digital Input capacitance Digital Output High Voltage Digital Output Low Voltage High-Z Leakage -100 0.2 100 nA DVdd -0.4V -1.0 -1.0 0.25 0.25 5 DVdd0.3V 0.3 0.4 V IOL = 1.5 mA 1.0 1.0 8 uA uA pF V IOH = 1.5 mA Internal pull-down resistor Internal pull-down resistor -5.0 50.0 0.05 90.0 5.0 125.0 nA uA Internal pull-up resistor -125.0 -125.0 -90.0 -90.0 -50.0 -50.0 uA uA Internal pull-down resistor Internal pull-down resistor -1.0 -1.0 0.05 -0.25 1.0 1.0 mA uA Internal pull-up resistor Min. 2.5 0.5 Typ. Max. Unit V V Conditions
DIGITAL INPUTS
DIGITAL OUTPUTS (CL = 10 pF)
Rev. P2.10
8
XRD64L42
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40 MSPS, 50% Duty Cycle, Differential Input Mode
Symbol Parameter Min. Typ. Max. Unit Conditions
POWER SUPPLIES AVDD DVDD Analog Power Supply Voltage Digital Power Supply Range Fs = 40 MHz, AVDD = DVDD = 2.7V, CL = 10pF, Fin = 10MHz (Includes Iref Current) AIDD DIDD DOIDD Analog Supply Current Digital Supply Current Output Driver Current 55 13 6 mA mA mA 2.7 AVDD 3.3 V DVDD = AVDD 2.7 3.0 3.3 V
PDISS Power Dissipation 200 mW Fs = 40 MHz, AVDD = DVDD = 3.3V, CL = 10pF, Fin = 10MHz (Includes Iref Current) AIDD DIDD DOIDD Analog Supply Current Digital Supply Current Output Driver Current 37 15 15 225 100 70 20 20 365 300 mA mA mA mW mA
PDISS Power Dissipation POWER DOWN CURRENT IPD Power Down Current
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2, 3 VDD to GND
Notes:
1
2
3
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. VDD refers to AVDD and DVDD. GND refers to AGND and DGND
Rev. P2.10
9

ESD
2000V min

VRT & VRB VIN All Inputs All Outputs Storage Temperature

VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V -65C to 150C
+7.0V
Lead Temperature (Soldering 10 seconds) 300C Maximum Junction Temperature 150C Package Power Dissipation Ratings (TA= +70C) TQFP GJA = 89.4C/W

XRD64L42
APPLICATION SECTION
Bandgap
XRD64L42
Voltage References The top ladder voltage for the XRD64L42 can be provided from an internal bandgap reference. The bandgap reference and its feedback path, Pins 1 and 2 respectively, can be used to set the voltage for VRHF. Select Rf and Ri (if gain is necessary) so that VRHF=VBG(1+Rf/Ri). The internal bandgap voltage is 1.24 volts. The XRD64L42 has a low impedence ladder, therefore, the typical value for Rf and Ri is 10K (Rf and Ri are recommended to be greater than 5K).See Figure 1. for a simplified diagram.
VBG AVdd VFBK
Direct Input
VRHF
Resistive Ladder
Direct Input
VRLF
Figure 3. Voltage Reference Provided by an External Source as Direct Inputs
Bandgap VBG VFBK Ri Rf VRHF
XRD64L42
Resistive Ladder
VRLF
Single-Ended Inputs The XRD64L42 can be used in either single-ended or differential input mode. For differential inputs, see the Differential Inputs Section. Single-ended inputs minimize the amount of external components necessary to interface with the XRD64L42. The common inputs, VINA(-) and VINB(-) should be tied to ground. VINA(+) and VINB(+) can be used to apply direct inputs to the XRD64L42. Figure 3. is a simplied diagram for singleended inputs. Pin 15, DIFF should be held low to select single-ended inputs.
Figure 2. Voltage Reference Generated from the Internal Bandgap Voltage External voltage references can be forced at VRHF and VRLF. If VRHF and VRLF are driven externally, VFBK should be connected to AVdd, which tri-states the bandgap reference. Direct inputs or inputs driven by external amplifiers can be used to drive the ladder reference voltages of the XRD64L42. See Figure 2. for a simplified diagram.
Input A 50
VINA(+) VINA(-)
Input B 50
VINB(+) VINB(-)
Figure 4. Single-Ended Inputs for the XRD64L42
Rev. P2.10
10
XRD64L42
Differential Inputs The XRD64L42 can be used in either differential or single-ended input mode. For single-ended inputs, see the Single-Ended Inputs Section. Differential inputs reduce system noise by removing noise components common at both input pins. Figure 4. is a simplified diagram that is used as a common test circuit with our XRD64L42/64L44EVAL application board. This circuit is used to evaluate the dynamic performance of the XRD64L42 using differential inputs. Pin 15, DIFF should be held high to select differential inputs. Auto-Calibration The XRD64L42 incorporates an auto-calibration circuit which continuously adjusts and matches the offset and linearity of each ADC. This auto-calibration circuit is transparent to the user after the initial 3.4ms calibration (168,000 initial clock cycles).
Note: To avoid auto-calibration after power down, do not disable CKIN. CKIN can be slowed down significantly to save power without losing calibration.
Input A
Transformer
22 VINA(+) VCMO VINA(-) 22
50
Input B
Transformer
22 VINB(+) VINB(-) 22
50
Figure 5. Common Test Circuit for the Differential Input Mode
SYNCO, Data Valid Delay and Latency SYNCO is an output pin provided by the XRD64L42. Valid data is available on the rising edge of SYNCO, see Figure 6. The Latency for the XRD64L42 is 17 clock cycles.
CKIN N N+1 N+2
Valid Data
N-17 tden=20ns
N-16
N-15
SYNCO tsynco=2ns (typical)
Figure 6. SYNCO, Data Valid Delay and Latency for the XRD64L42
Rev. P2.10
11
XRD64L42
Rev. P2.10
VIN A 6 0 4 1 2 22 3 22 Tra ns f orm e r 50 AGN D VIN B 6 0 4 1 2 3 22 22 10 pF Tra ns f orm e r 50 AGN D 10 pF
0. 2 uF Note: VRHF=1.25[(10K/10K)+1]=2.5V 0. 1 uF 10 K 10 K 2u F 5 6 AGN D 58 59 49 56 55 10 pF 0. 1 uF +3 . 0V AGN D 52 61 62 13 41 10 pF 24 39 AGN D 10 11 25 42 50 23 40 0. 1 uF 0. 1 uF 0. 1 uF 0. 1 uF 0. 1 uF 0. 1 uF 0. 1 uF AGN D AGN D D OVD D D OVD D D GN D D GN D D GN D D GN D D GN D D OGN D D OGN D 1 2 3 4 VBG VF BK VR H F VR H F V R LF V R LF VIN A+ VIN AV C MO VIN B+ VIN BD A0 D A1 D A2 D A3 D A4 D A5 D A6 D A7 D A8 D A9 O TR A D B0 D B1 D B2 D B3 D B4 D B5 D B6 D B7 D B8 D B9 O TR B 34 35 36 37 38 43 44 45 46 47 48 20 21 22 26 27 28 29 30 31 32 33 18 19 12 15 17 14 7 8 9 16 51 53 54 57 60 63 64 D A0 D A1 D A2 D A3 D A4 D A5 D A6 D A7 D A8 D A9 O TR A D B [ 9: 0] , O TR B D B0 D B1 D B2 D B3 D B4 D B5 D B6 D B7 D B8 D B9 O TR B D A [ 9: 0] , O TR A
XRD64L42
AVD D AVD D AVD D D VD D D VD D
C KIN SY N C O PD D IF F TR I _A TR I _B AGN D AGN D AGN D AGN D AGN D AGN D AGN D AGN D AGN D AGN D AGN D
C KIN SY N C O D IF F
12
+3 . 0V Note: bypass capacitors for pins 13, 24, 39, 41, 52, 61, 62
AGN D
+3 . 0V Note: bypass capacitors for pins 13, 24, 39, 41, 52, 61, 62
0. 0 1uF
0. 0 1uF
0. 0 1uF
0. 0 1uF
0. 0 1uF
0. 0 1uF
0. 0 1uF
AGN D
Figure 7. Typical Application Circuit for the XRD64L42 Operating in Differential Mode
XRD64L42
XRD6442 DIFFERENTIAL NONLINEARITY ERROR Fc = 40MHz
0.8
0.8 0.6 DNL Error in LSB 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 1 51 101 151 201 251 301 351 401 451 501 551 601 651 701 751 801 851 901 951 1001
XRD6442 INTEGRAL NONLINEARITY
INL ERROR in LSB
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
OUTPUT CODE
OUTPUT CODE
Figure 8. Differential Non-Linearity, Differential Input Mode, Fc=40MHz, Fin=1.5kHz, VRHF=2.5V, VDD=3V
Figure 9. Integral Non-Linearity, Differential Input Mode, Fc=40MHz, Fin=1.5kHz, VRHF=2.5V, VDD=3V
XRD64L42 IMD
Fin1 = 2.51Mhz, Fin2 = 3.4375Mhz
8192-Point FFT, Fclock =40.0MHz, Differential input mode
0.00 -10.00 -20.00 -30.00 -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00 -110.00 -120.00 0.957 1.919 2.881 3.843 4.805 5.767 6.729 7.690 8.652 9.614 10.576 11.538 12.500 13.462 14.424 15.386 16.348 17.310 18.271 19.233 Fbin
XRD64L42 Crosstalk Fs=40MSPS Singel-Ended and Differential Modes Channel 1=1MHz, Channel 2=(1.5MHz-10.5MHz)
0 Crosstalk (dB) -20 -40 -60 -80 -100 1.5 3 4.5 6 Differential Input Single-Ended Input
Relative Power in db
7.5
9
10.5
Input Frequency (MHz)
Frequency
Figure 10. Intermodulation Distortion, Fin1=2.51MHz, Fin2=3.4375MHz, 8192-point FFT, Fc=40MHz, Differential Input Mode
Figure 11. Crosstalk vs Input Frequency, VDD=3V, Differential and Single Ended Inputs
Rev. P2.10
13
XRD64L42
0 SingleTone 8192 Point FFT SFDR -71.19 SINAD -59.89
0 SingleTone 8192 Point FFT SFDR -73.18 SINAD -59.77
-20
-20
-40 Relative Power in dB Relative Power in dB DC 2.4 4.9 7.3 9.8 12.2 14.6 17.1 19.5
-40
-60
-60
-80
-80
-100
-100
-120
-120
-140
-140
-160 Frequency in MHz
-160 DC 2.4 4.9 7.3 9.8 12.2 14.6 17.1 19.5 Frequency in MHz
Figure 12. FFT Spectrum @Fclock = 40.0MHz, Fin = 1.0MHz, DIFFERENTIAL INPUT MODE
Figure 13. FFT Spectrum @Fclock = 40.0MHz, Fin = 4.0MHz, DIFFERENTIAL INPUT MODE
0 SingleTone 8192 Point FFT SFDR -67.12 SINAD -58.28
SNR vs Input Frequency
-20
70.00 Relative Power in dB 60.00 50.00
Single-ended Differential Input
-40 Relative Power in dB
-60
-80
40.00 30.00 20.00 10.00 0.00 10 14 0 1 2 3
ClockRate: 40MHz AVDD,DVDD @3.0v
-100
-120
-140
-160 DC 2.4 4.9 7.3 9.8 12.2 14.6 17.1 19.5 Frequency in MHz
fIN (MHz)
Figure 14. FFT Spectrum @Fclock = 40.0MHz, Fin = 10.0MHz, DIFFERENTIAL INPUT MODE
Figure 15. SNR vs Input Frequency, Differential and Single Ended Inputs, VDD=3V
Rev. P2.10
14
30
4
5
7
8
XRD64L42
SINAD vs Input Frequency
70
Supply Current vs Sample Clock Frequency
70.00 Relative Power in dB 60.00 50.00
Single-ended Dif f erent ial Input
AIDD
60 Supply Current (mA) 50 40 30
TA=25C, 1MHz40.00 30.00 20.00 10.00 0.00 10 30 0 2 4 7 fIN (MHz)
ClockRat e: 40MHz AVDD,DVDD @3.0v
20 10
DOIDD
0 10 15 20 25 30 35 40 45 50 55 60
fs (MSPS)
Figure 16. SINAD vs Input Frequency, Differential and Single Ended Inputs, VDD=3V
Figure 17. Supply Current vs Sample Clock Frequency
VCMO and VBG vs Temp
1.26 VCMO 1.255
26. 3 26. 5
R i vs T em p erature n
26. 4
(Voltage)
1.25 VBG 1.245
26. 2
26. 1
26
25. 9
1.24 @VDD=3.0V 1.235 -40 +25 Temp (Degree C) +85
25. 8
25. 7 40 + 25 T em p. (C ) + 85
Figure 18. VCMO and VBG vs Temperature
Figure 19. Rin of VINA+, VINB+ vs Temperature at Fc=40MSPS
Rev. P2.10
15
XRD64L42
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2000 EXAR Corporation
Datasheet January 2001 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. P2.10
16

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